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Forward error correction (FEC) technologies

FECs offered for virtually any link requirement

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Viasat’s experience in advanced physical layer technologies and in-house development makes us a one-stop FEC shop. Our forward error correction solutions include a diversified portfolio of software, DSP, FPGA, and ASIC implementations for FEC modems in satellite, mobile, and optical communications systems.

Advanced FEC codes for optical communications

Proven modules

We have developed and implemented proven FEC forward error correction modules that are necessary to achieve 100 to 800 Gbps throughput, and have the highest net effective coding gain based on the size of the core and the data rates.

Range of products

FEC technologies include high gain turbo product code (TPC), low density parity check (LDPC), and Bose-Chaudhuri-Hocquenghem (BCH). Our products include IP cores for FPGAs and ASICs.

TPCs for optical communications

Viasat 66200 SDFEC (soft decision forward error correction) is a family of turbo product codes (TPC) designed for use in high speed optical communications (100, 200, 400, 800G). With either 7% or 20% overhead, TPCs are the optimum FEC for high data rate, high coding gain applications where low latency and high net equivalent coding gain (NECG) are desired.

FEC code types

Find what you need

Random error-correcting cyclic codes

BCH codes form a large class of powerful random error correcting cyclic codes. These FEC codes are used as component codes for building more powerful codes and as an error floor removal tool.

We have implemented encoders/decoders for a variety of different size and correction capacity BCH codes using different algebraic decoding options. The BCH codecs flexible design can be readily extended to support different block sizes and correction capacities than our current configurations.

Available configurations:

Serial number	FEC type	Decoding type	Block size (bits)	Code rate(s)	Implementation device	Maximum speed (line rate)
1)	BCH	Hard-decision	16383	t<=12	ASIC / Intel FPGA / Xilinx FPGA	800 Mbps
1)	BCH	Hard-decision	65535	t<=12	ASIC / Intel FPGA / Xilinx FPGA	800 Mbps
2)	BCH	Hard-decision / Soft-decision	16	t<=1,2,(3)	ASIC / Intel FPGA / Xilinx FPGA	200 Mbps
			32
			64
			128
			256

Serial or parallel concatenated convolution code

CTCs use highly-powerful iterative decoding to achieve performance close to coding theory limits. They employ serial or parallel concatenated convolution code with pseudo-random interleaving between the inner and outer code. CTCs perform extremely well at lower code rates and have been used in a variety of telecommunication standards including DVB-RCS.

We have developed a DSP as well as FPGA implementation for the DVB-RCS CTC. This implementation can be easily extended to suit other CTC configurations.

Serial number	FEC type	Decoding type	Block size (bits)	Code rate(s)	Implementation device	Maximum speed (line rate)
1)	DVB-RCS CTC	Soft-decision	96 (info)	1/2, 2/3, 3/4, 5/6, and 7/8	Xilinx Virtex-2 Pro / DSP	Up to 10 Mbps
			128 (info)	1/2, 2/3, 3/4, 5/6, and 7/9
			424 (info)	1/2, 2/3, 3/4, 5/6, and 7/10
			440 (info)	1/2, 2/3, 3/4, 5/6, and 7/11
			456 (info)	1/2, 2/3, 3/4, 5/6, and 7/12
			848 (info)	1/2, 2/3, 3/4, 5/6, and 7/13
			864 (info)	1/2, 2/3, 3/4, 5/6, and 7/14
			880 (info)	1/2, 2/3, 3/4, 5/6, and 7/15
			1696 (info)	1/2, 2/3, 3/4, 5/6, and 7/16
			1712 (info)	1/2, 2/3, 3/4, 5/6, and 7/17
			1728 (info)	1/2, 2/3, 3/4, 5/6, and 7/18
			1504 (info)	1/2, 2/3, 3/4, 5/6, and 7/19

FEC defined by very sparse parity check matrices

LDPC is a powerful FEC option that is defined by very sparse parity check matrices. LDPC designs allow for parallel iterative decoder processing, which can be implemented in a hardware-friendly fashion while maintaining excellent performance close to the Shannon limit. These cores use our proprietary, efficient, and scalable architectures for implementing LDPC encoders and decoders.

Available LDPC products:

Serial number	FEC type	Decoding type	Block size (bits)	Code rate(s)	Implementation device	Maximum speed (line rate)
1)	DVB-S2 LDPC	Soft-decision	16200	1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6, 8/9	ASIC / Altera Stratix FPGA / Xilinx Virtex-4 FPGA	800 Mbps with 270 MHz clock
1)	DVB-S2 LDPC	Soft-decision	64800	1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6, 8/9, 9/10	ASIC / Altera Stratix FPGA / Xilinx Virtex-4 FPGA	800 Mbps with 270 MHz clock
2)	Proprietary LDPC	Soft-decision	16200	1/2, 2/3, 3/4, 4/5, 5/6	Xilinx Virtex-4 60 and 100	100 Mbps with 200 MHz clock
3)	CCS DS LDPC	Soft-decision	8176	7/8	Xilinx Virtex-5 330	1.4 Gbps with 150 MHz clock
4)	CCS DS LDPC	Hard-decision	8176	7/8	Xilinx Virtex-5 330	1.4 Gbps with 150 MHz clock

Inner and outer codes with different FEC types

Our implementation of other heterogeneous concatenated codes feature inner and outer codes with different FEC types. That enables you to take advantage of the strong points of different FEC types, resulting in concatenated codes with exceptional performance.

Heterogeneous concatenated code designs:

Serial number	FEC type	Decoding type	Block size (bits)	Code rate(s)	Implementation device	Maximum speed (line rate)
1)	DVB-S2 LDPC + BCH	Soft-decision	16200	1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6, 8/9	ASIC / Altera Stratix FPGA / Xilinx Virtex-4 FPGA	800 Mbps
1)	DVB-S2 LDPC + BCH	Soft-decision	64800	1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6, 8/9, 9/10	ASIC / Altera Stratix FPGA / Xilinx Virtex-4 FPGA	800 Mbps
2)	Proprietary LDPC + BCH	Soft-decision	16200	1/2, 2/3, 3/4, 4/5, 5/6	Xilinx Virtex-4 FPGA	100 Mbps
13)	TPC + RS	Hard-decision	130560	0.5	Xilinx Virtex-5 FPGA	2.5 Gbps

Powerful non-binary cyclic codes

Reed Solomon codes form a large class of powerful non-binary cyclic codes. The non-binary symbol-based nature of RS codes makes them suitable for correcting correlated error events. As RS codes make corrections on a symbol by symbol basis, correlated bit errors that fall into a symbol get corrected together. These FEC codes are used as component codes for building more powerful codes like RS-TPCs or RSPs and also as an error floor removal tool in concatenated codes.

We have implemented encoders/decoders for different size and correction capacity RS codes using different algorithms. The RS codec's flexible design can be extended to support different block sizes and correction capacities than in current configurations as well.

Serial number	FEC type	Decoding type	Block size (bits)	Code rate(s)	Implementation device	Maximum speed (line rate)
1)	RS	Hard-decision	2040	0.937254902	Xilinx Virtex-5 200	1.4 Gbps
2)	RS	Hard-decision	2040	0.937354902	Xilinx Virtex-5 200	10 Gbps
3)	RS	Hard-decision	32640	0.9375	Xilinx Virtex-5 200	10 Gbps

Random error-correcting cyclic codes

BCH codes form a large class of powerful random error correcting cyclic codes. These FEC codes are used as component codes for building more powerful codes and as an error floor removal tool.

We have implemented encoders/decoders for a variety of different size and correction capacity BCH codes using different algebraic decoding options. The BCH codecs flexible design can be readily extended to support different block sizes and correction capacities than our current configurations.

Available configurations:

Serial number	FEC type	Decoding type	Block size (bits)	Code rate(s)	Implementation device	Maximum speed (line rate)
1)	TPC	Soft-decision	16384	0.779	Xilinx Virtex-4 FPGAs	1.2 Gbps
			32768	0.85, 0.824
			65536	0.93, 0.87
2)	TPC + RS	Soft-decision	1024	0.66	ASIC / Xilinx Virtex-4 FPGAs	1.5 Gbps
			4096	0.325, 0.495, 0.635, 0.717, 0.793
			8192	0.384, 0.423, 0.467, 0.578, 0.703, 0.747, 0.786, 0.835
			16384	0.367, 0.404, 0.454, 0.511, 0.532, 0.619, 0.633, 0.779, 0.828, 0.879